This invention relates generally to photolithography for semiconductor processing, and more particularly to electron beam (e-beam) aligners used in such photolithography.
Patterning is one of the basic steps performed in semiconductor processing. It also referred to as photolithography, masking, oxide or metal removal, and microlithography. Patterning enables the selective removal of material deposited on a semiconductor substrate, or wafer, as a result of a deposition process. For example, as shown in FIG. 1A, a layer 104 has been deposited on a substrate 102. After the photolithography process is performed, as shown in FIG. 1B, some parts of the layer 104 have been selectively removed, such that gaps 106a and 106b are present within the layer 104. A photomask, or pattern, is used (not shown in FIG. 1B) so that only the material from the gaps 106a and 106b are removed, and not the other portions of the layer 104.
The process of adding layers and removing selective parts of them, in conjunction with other processes, permits the fabrication of semiconductor devices. Alignment is critical in photolithography and deposition, as well as in other semiconductor processes. If layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, relegating them to scrap, which can be costly.
One type of aligner that can be used in photolithography is the electron beam, or e-beam aligner. Electron beam lithography is used in the production of high-quality masks and reticles, as well as in the direct patterning of wafers. An e-beam system includes an electron source that produces a small diameter spot, or shot, and a blanker capable of turning the beam on and off. The exposure takes place in a vacuum to prevent air molecules from interfering with the electron beam. The beam passes through electrostatic plates capable of directing, or steering, the beam in the x and y directions on the mask, reticle, or wafer. Precise direction of the beam usually requires that the beam travel in a vacuum chamber in which there is the electron beam source, support mechanisms, and the substrate being exposed.
Since the desired pattern is generated by a computer, there typically is no mask in e-beam lithography. The beam is directed to specific positions on the wafer surface by a deflection subsystem, and the beam turned on where the resist is to be exposed. Larger substrates are mounted on an x-y stage and are moved under the beam to achieve full surface exposure. This alignment and exposure technique is referred to as direct writing.
The pattern is exposed in the resist layer of the wafer by either raster or vector scanning, which are shown in FIGS. 2A and 2B, respectively. In FIG. 2A, the beam 204 is moved on the wafer 202 as indicated by the arrowed line 206, side-to-side and down the wafer 202. A computer directs the movement and activates the blanker in regions where the resist is to be exposed. A drawback to raster scanning is the time required for the beam to scan, since it travels over the entire surface of the wafer 202. By comparison, in FIG. 2A, the beam is moved on the wafer 202 directly to the regions that have to be exposed, such as from position 208A, to position 208B, and then to position 208C. At each position, small square- or rectangular-shaped areas are exposed, building up the desired shape of the exposed area.
Furthermore, since the invention of the integrated circuit (IC), semiconductor chip features that are patterned using photolithography techniques such as e-beam lithography have become exponentially smaller and the number of transistors per device exponentially larger. Advanced IC""s with hundreds of millions of transistors at feature sizes of 0.25 micron, 0.18 micron, 0.13 micron, and less are becoming routine. To continue to make chip features smaller, and increase the transistor density of semiconductor devices, IC""s have begun to be manufactured that have features smaller than the lithographic wavelength.
Sub-wavelength lithography, however, places large burdens on lithographic processes. Resolution of anything smaller than a wavelength is generally quite difficult. Pattern fidelity can deteriorate dramatically in sub-wavelength lithography. The resulting semiconductor features may deviate significantly in size and shape from the ideal pattern drawn by the circuit designer. These distortions include line-width variations dependent on pattern density, which affect a device""s speed of operation, and line-end shortening, which can break connections to contacts. To avoid these and other proximity effects, the semiconductor industry has attempted to compensate for them in the photomasks themselves.
This compensation is generally referred to as optical proximity correction (OPC). The goal of OPC is to produce smaller features in an IC using a given equipment set by enhancing the printability of a wafer pattern. OPC applies systematic changes to mask geometries to compensate for the nonlinear distortions caused by optical diffraction and resist process effects. A mask incorporating OPC is thus a system that negates undesirable distortion effects during pattern transfer. OPC works by making small changes to the IC layout that anticipate the distortions. OPC offers basic corrections and a useful amount of device yield improvement, and enables significant savings by extending the lifetime of existing lithography equipment. Distortions that can be corrected by OPC include line-end shortening and corner rounding, among others.
For photomasks having features of 0.13 micron or smaller in particular, OPC is aggressively used to ensure that the features are properly printed on the wafer or mask. When such masks or wafers used with e-beam photolithography, this means that shots of extremely small sizes are unavoidable for proper e-beam exposure. Nearly all e-beam systems exhibit some proximity effects. Such small shots are necessary to achieve proper critical dimensioned features, where critical dimensions are the widths of the lines and spaces of critical circuit patterns and the areas of critical contacts.
A source of error that can affect critical dimension uniformity and mean values is poor e-beam shot linearity. E-beam shot linearity is the degree to which the relative sizes of e-beam shots, or spots, deviate from their intended size. Like other errors that occur in semiconductor fabrication, poor e-beam shot linearity must be measured and monitored in order for it to be compensated and properly patterned semiconductor wafers to be subsequently produced. Unfortunately, however, deficiency in e-beam shot size linearity is generally measured or monitored only with difficulty. Linearity deficiency is more specifically difficult to be isolated from other error sources. This inability to measure the lack of e-beam linearity means that linearity deficiencies cannot subsequently be easily corrected or compensated for, resulting in improperly patterned semiconductor wafers.
Therefore, there is a need to accurately monitor e-beam shot size linearity deficiency. Such monitoring should desirably be able to isolate such linearity deficiency from other sources of errors. Furthermore, such monitoring should desirably enable subsequent correction or compensation for the linearity deficiency, resulting in more properly patterned semiconductor wafers. For these and other reasons, there is a need for the present invention.
The invention relates to monitoring electron beam (e-beam) shot linearity. A pattern is written that has a predetermined size and a predetermined form in a predetermined position on a substrate, such as a semiconductor wafer or a reticle (i.e. a photomask). The pattern writing fixes the e-beam shot size, as located along one or more critical dimensions of the pattern. The critical dimensions are then measured, where their variations reflect the e-beam shot size linearity. Thereafter, deficiencies in the e-beam shot size linearity can be compensated for, to allow for properly produced semiconductor patterns.
The invention provides for advantages over the prior art. By using the invention, e-beam capability as to shot size control can be determined. The error caused by e-beam shot size instability may be defined, and shot size stability may be subsequently optimized. An optimal shot range for critical dimension uniformity control can be defined, and more suitable optical proximity correction (OPC) rules may be defined that avoid too small features. Furthermore, the shot size linearity data that is measured can be used to modify the e-beam dissection mode to avoid shot sizes having poor linearity. Still other advantages, embodiments, and aspects of the invention will become apparent by reading the detailed description that follows, and by referencing the attached drawings.